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Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 18 LVCMOS/LVTTL outputs * Selectable LVCMOS_CLK or LVPECL clock inputs * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency: 250MHz * Output skew: 150ps (maximum) * Part to part skew: 750ps (maximum) * Additive phase jitter, RMS: < 0.03ps (typical) * Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes * 0C to 70C ambient operating temperature * Lead-Free package available * Pin compatible with the MPC940L
GENERAL DESCRIPTION
The ICS83940D is a low skew, 1-to-18 LVPECLto-LVCMOS/LVTTL Fanout Buffer and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines.
ICS
The ICS83940D is characterized at full 3.3V and 2.5V or mixed 3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940D ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
GND VDDO Q0 Q1 Q2 Q3 Q4 Q5
CLK_SEL PCLK nPCLK LVCMOS_CLK GND 18 Q0:Q17
1
32 31 30 29 28 27 26 25
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO
24 23 22
Q6 Q7 Q8 VDD Q9 Q10 Q11 GND
GND LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO
ICS83940D
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Pacakge Top View
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Name GND Power Input Input Input Input Power Power Output Type Description Power supply ground. Pulldown Clock input. LVCMOS / LVTTL interface levels. Clock select input. Selects LVCMOS / LVTTL clock Pulldown input when HIGH. Selects PCLK, nPCLK inputs when LOW. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. Pulldown VDD/2 default when left floating. Core supply pins. Output supply pins. Clock outputs. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 12, 17, 25 3 4 5 6 7, 21 8, 16, 29 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32
LVCMOS_CLK CLK_SEL PCLK nPCLK VDD VDDO Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN C PD RPULLup RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 18 Test Conditions Minimum Typical 4 6 51 51 28 Maximum Units pF pF K K
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 PCLK, nPCLK Selected De-selected Clock LVCMOS_CLK De-selected Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK_SEL 0 0 0 0 0 0 1 1
83940DY
Outputs PCLK 0 1 0 1 nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- -- Q0:Q17 LOW HIGH LOW HIGH HIGH LOW LOW HIGH
LVCMOS_CLK -- -- -- -- -- -- 0 1
Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended
Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting Non Inver ting
REV. B JUNE 15, 2004
Biased; NOTE 1 Biased; NOTE 1 -- --
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
3.6V -0.3V to VDD + 0.3V -0.3V to VDDO + 0.3V 20mA -40C to 125C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Input Current, IIN Storage Temperature, TSTG
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Test Conditions LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK PCLK, nPCLK 500 VDD - 1.4 Minimum 2.4 Typical Maximum VDD 0.8 1000 VDD - 0.6 200 IOH = -20mA IOL = 20mA 2.4 0.5 25 Units V V mV V A V V mA
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = 0 TO 70
Symbol Parameter VIH VIL V PP VCMR IIN VOH VOL Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current Output High Voltage Output Low Voltage
Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = 0 TO 70
Symbol fMAX tpLH Parameter Output Frequency Propagation Delay PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 0.03 0.5 to 2.4V f < 134MHz 0.3 45 50 1.1 55 1.6 1.8 1.6 1.8 Test Conditions Minimum Typical Maximum 250 3.0 3.0 3.3 3.2 150 150 1.4 1.2 1.7 1.4 850 750 Units MHz ns ns ns ns ps ps ns ns ns ns ps ps ps ns %
tpLH
Propagation Delay
tsk(o) tsk(pp) tsk(pp) tsk(pp) tjit
tR / tF odc
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 4, 5
PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time Output Duty Cycle
134MHz f 250MHz 40 50 60 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7: Driving only one input clock.
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Test Conditions LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK PCLK, nPCLK 300 VDD - 1.4 Minimum 2.4 Typical Maximum VDD 0.8 1000 VDD - 0.6 200 IOH = -20mA IOL = 20mA 1.8 0.5 25 Units V V mV V A V V mA
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0 TO 70
Symbol Parameter VIH VIL V PP VCMR IIN VOH VOL Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current Output High Voltage Output Low Voltage
Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0 TO 70
Symbol Parameter fMAX tpLH Output Frequency Propagation Delay PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 0.03 0.5 to 1.8V 0.3 1.2 1.7 1.7 1.6 1.8 Test Conditions Minimum Typical Maximum 250 3.2 3.0 3.4 3.3 150 150 1.5 1.3 1.8 1.5 850 750 Units MHz ns ns ns ns ps ps ns ns ns ns ps ps ps ns
tpLH
Propagation Delay
tsk(o) tsk(pp) tsk(pp) tsk(pp) tjit
tR / tF
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 4, 5
PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time
odc Output Duty Cycle f < 134MHz 45 50 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7: Driving only one input clock.
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Test Conditions LVCMOS_CLK LVCMOS_CLK PCLK, nPCLK PCLK, nPCLK 300 VDD - 1.4 Minimum 2 Typical Maximum VDD 0.8 1000 VDD - 0.6 200 IOH = -12mA IOL = 12mA 1.8 0.5 25 Units V V mV V A V V mA
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VIH VIL V PP VCMR IIN VOH VOL Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Input Common Mode Voltage; NOTE 1, 2 Input Current Output High Voltage Output Low Voltage
Core Supply Current IDD NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter fMAX Output Frequency tpLH Propagation Delay; PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK; NOTE 1, 5 LVCMOS_CLK; NOTE 2, 5 PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK PCLK, nPCLK LVCMOS_CLK Test Conditions f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 f 150MHz f 150MHz f > 150MHz f > 150MHz Measured on rising edge @VDDO/2 0.03 0.5 to 1.8V 0.3 1.2 Minimum Typical Maximum 200 3.8 3.2 3.7 3.6 200 200 2.6 1.7 2.2 1.7 1.2 1.0 Units MHz ns ns ns ns ps ps ns ns ns ns ns ns ps ns
1.2 1.5 1.5 2
tpLH
Propagation Delay;
tsk(o) tsk(pp) tsk(pp) tsk(pp) tjit
tR / tF
Output Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 6 Par t-to-Par t Skew; NOTE 4, 5
PCLK, nPCLK LVCMOS_CLK Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 7 Output Rise/Fall Time
odc Output Duty Cycle f < 134MHz 45 55 % All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output VDDO/2. NOTE 2: Measured from VDD/2 to VDDO/2. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 7 Driving only one input clock.
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
at 155.52MHz = 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
V DD VDDO
SCOPE
LVCMOS
GND
Qx
LVCMOS
GND
Qx
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
V DD
VDD, VDDO
SCOPE
nPCLK V PCLK
PP
LVCMOS
GND
Qx
Cross Points
V
CMR
GND -1.25V5%
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
V
DDO
V
DDO
Qx PART 2
2
Qx
2
V
V
DDO
DDO
Qy
2
Qy
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
83940DY
OUTPUT SKEW
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
V
DD
LVCMOS_CLK nPCLK PCLK
2
2.4V
2.4V
V
DDO
Q0:Q17
t
PD
2
0.5V Clock Outputs t
R
0.5V t
F
PROPAGATION DELAY
3.3V OUTPUT RISE/FALL TIME
1.8V
1.8V
0.5V Clock Outputs t
R
0.5V t
F
2.5V OUTPUT RISE/FALL TIME
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
3.3V
3.3V 3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 2F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
67.8C/W 47.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940D is: 820
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead Free" LQFP 32 Lead "Lead Free" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83940DY ICS83940DYT ICS83940DYLF ICS83940DYLFT Marking ICS83940DY ICS83940DY ICS83940DYLF ICS83940DYLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83940DY
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REV. B JUNE 15, 2004
Integrated Circuit Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table T5A
Page 4
A
Description of Change 3.3V AC Characteristics table * tsk(pp) Test Conditions, replaced "<" with " "; corrected Units to "ns" from "ps". * odc - corrected Test Conditions to read "134MHz f 250MHz", from "f 250MHz". 3.3V/2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced "<" with " "; corrected Units to read "ns" from "ps". 2.5V AC Characteristics table - tsk(pp) Test Conditions, replaced "<" with " "; corrected Units to "ns" from "ps". Pin Characteristics table - changed ROUT 25 maximum to 28 maximum. Delete RPULLUP row. 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read -1.65V... from -1.165V... Added LVTTL to title. Updated format. Pin Description Table - added Pullup and Pulldown to Pin 6, nPCLK. Pin Characteristics Table - added RPULLUP row. Added tjit row. Added tjit row. Added tjit row. Added Additive Phase Jitter section. Updated Single Ended Signal Driving Differential Input diagram. Added LVPECL Clock Interface section. Added "Lead-Free" bullet to Features section. Added NOTE 7. Updated LVPECL Clock Input Interface section. Ordering Information table - added "Lead-Free" par t number.
Date
T5B T5C T2
5 6 2 7
10/11/02
A
12/12/02
T1 T2 B T5A T5B T5C
B
T5A - T5C
2 2 4 5 6 7 10 11 1 4-6 11 14
10/9/03
6/15/04
83940DY
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